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| UT1553B RTI Remote Terminal Interface FEATURES E Complete MIL-STD-1553B Remote Terminal E E E E interface compliance Dual-redundant data bus operation supported Internal illegalization of selected mode code commands External illegal command definition capability Automatic DMA control and address generation E Operational status available via dedicated lines or internal status register E ASD/ENASC (formerly SEAFAC) tested and approved E Available in ceramic 84-lead leadless chip carrier and 84-pin pingrid array E Full military operating temperature range, -55C to +125C, screened to the specific test methods listed in Table I of MIL-STD-883, Method 5004, Class B E JAN-qualified devices available MODE CODE/ SUB ADDRESS MIL-STD-1553B SERIAL BUS TRANSCEIVER I/O IN DECODER CHANNEL A ILLEGAL COMMAND HOST SYSTEM ADDRESS INPUTS MEMORY ADDRESS CONTROL OUTPUT MULTIPLEXING AND SELF TEST WRAP-AROUND LOGIC A OUT OUTPUT EN COMMAND RECOGNITION LOGIC MEMORY ADDRESS OUTPUTS DECODER CHANNEL B CONTROL AND ERROR LOGIC CONTROL INPUTS CONTROL OUTPUTS TIMEOUT MUX DATA TRANSFER LOGIC CLOCK AND RESET LOGIC 12MHz TIMERON IN B ENCODER OUT RESET 16 2MHz DATA I/O BUS Figure 1. UT1553B RTI Functional Block Diagram RTI-1 Table of Contents 1.0 ARCHITECTURE AND OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1.1 Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1.2 Transparent Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Mode Codes and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 MIL-STD-1553B Subaddress and Mode Codes . . . . . . . . . . . . . . . . . . . . . . . .9 Remote Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 MEMORY MAP EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 PIN IDENTIFICATION AND DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 MAXIMUM AND RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . 21 5.0 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.0 AC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.0 PACKAGE OUTLINE DRAWINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 RTI-2 1.0 ARCHITECTURE AND OPERATION The UT1553B RTI is an interface device linking a MILSTD-1553 serial data bus and a host microprocessor system. The RTI's MIL-STD-1553B interface includes encoding/ decoding logic, error detection, command recognition, memory address control, clock, and reset circuits. Output Multiplexing and Self-Test Logic This logic directs the output of the encoder to one of four places:- Channel A outputs - Channel B outputs - Channel A decoders during self-test - Channel B decoders during self-test Clock and Reset Logic The UT1553B RTI requires a 12MHz input clock to operate properly. The RTI provides a 2MHz output for the system designer to use. The device provides a hardware reset pin as well as software-generated reset. Timer Logic The UT1553B RTI has a built-in 730ms timer that is activated when the encoder is about to transmit. The timer is reset upon receipt of a valid command, master reset, or a time-out condition. 1.1 HOST INTERFACE Configure the RTI into the host system for either a direct memory or transparent memory access. The following sections discuss the system configuration for each method of memory management. 1.1.1 Direct Memory Access In the direct memory access configuration the RTI and host arbitrate for the shared 2K x 16 memory space. To request access to memory the RTI asserts direct memory request output (DMARQ); the system bus arbiter grants the RTI access to memory by asserting the direct memory access grant signal (MEMCK). The system arbiter should not assert the MEMCK signal before the RTI has requested access to memory (i.e., DMARQ asserted). Once granted access to memory, the RTI address out (ADDR OUT(10:0)), RAM chip select (RCS), RAM read/ write (RRD/RWR), and Data bus (DATA I/O(15:0)) provide the interface signals to control the memory access. Figure 2 shows an example of a direct memory access system configuration; for clarity the interface buffers and logic are excluded. The host microprocessor also gains access to memory by arbitration. Take care to insure that bus contention does not occur between the host and RTI Address buses or memory control signals. To place the RTI Address Out bus in a high impedance state negate the ADOEN input pin. Also note that outputs RCS and RRD/RWR are not three-state outputs. When the RTI is not writing to memory, bidirectional Data bus DATA I/O(15:0) is an input (i.e., not actively driving the bus). Decoders The UT1553B RTI contains two separate free-running decoders to insure that all redundancy requirements of MILSTD-1553B are met. Each decoder receives, decodes, and verifies biphase Manchester II data. Proper frequency and edge skew are also verified. Command Recognition Logic The command recognition logic monitors the output of both decoders at all times. Recognition of a valid command causes a reset of present interface activity followed by execution of the command. This procedure meets the requirement for superseding valid commands. Encoder The encoder receives serial data from the data transfer logic, converts it to Manchester II form with proper synchronization and parity, and passes it to the output and self-test logic. Data Transfer Logic The data transfer logic provides double-buffered 16-bit parallel-to-serial and serial-to-parallel conversion during reception and transmission of data. Memory Address Control The memory address control logic controls the output of the three-state address lines during memory access. In DMA system implementations, the memory address control provides RTI-generated addresses. In a pseudo-dual-port memory configuration, the memory address control logic provides either RTI-generated or host system addressing. Control and Error Logic The control and error logic performs the following four major functions: - Interface control for proper processing of MILSTD-1553B commands Error checking of both MIL-STD-1553B data and RTI operation Memory control (DMA or pseudo-dual-port) for proper data transfer Operational status and control signal generation RTI-3 Shared Memory CONTROL DATA(15:0) ADDR(10:0) CONTROL Host Computer RTI UT1553B DMA CONTROLLER Figure 2. Direct Memory Access Configuration The host microprocessor gains access to the RTI internal registers by controlling input pins CS, CTRL, ADDR IN (10:0), and RD/WR. During message processing the host microprocessor should limit access to RTI internal registers. 1.1.2 Transparent Memory Access Configured in the transparent memory mode the host microprocessor accesses shared memory through the RTI. Arbitration for access to the bus is performed as discussed in section 1.1.1 of this document. When granted access to memory, the RTI asserts memory control signals ADDR OUT(10:0), RCS, and RRD/RWR. For host-controlled memory accesses the RAM memory address from the host is propagated from the Address In bus ADDR IN (10:0) to the Address Out bus ADDR OUT (10:0). Memory control signals RD/WR and CS are also propagated through the RTI as RRD/RWR and RCS. Input CTRL is negated during all transparent memory accesses to prevent the RTI from inadvertently performing an internal register access or software reset. While CS is asserted, the RTI's bidirectional Data bus DATA I/O (15:0) is an input (i.e., not actively driving bus). The host microprocessor gains access to the RTI internal registers by controlling input pins CS, CTRL, ADDR IN (10:0), and RD/WR. During message processing the host microprocessor should limit access to RTI internal registers. The host should not assert CS while the RTI is performing a memory access. 1.2 Internal Register Description The RTI uses three internal registers to allow the host to control the RTI operation and monitor its status. The host uses the following inputs Control (CTRL), Chip Select (CS), Read/Write (RD/WR), and ADDR IN (0) to read the 16-bit System Register or write to the 8-bit Control Register. The Control Register toggles bits in the MIL-STD-1553B status word, enables biphase inputs, selects terminal active flag, and puts the part in self-test. The System Register supplies operational status of the UT1553B RTI to the host. The Last Command Register saves the command word for a Transmit Last Command mode code, along with operational status from the System Register. DATA(15:0) Host Computer CONTROL DATA I/O (15:0) ADDR IN (10:0) RTI UT1553B CONTROL ADDR OUT (10:0) Shared Memory DMA CONTROLLER Figure 3. Transparent Memory Access Configuration Control Register (Write Only) RTI-4 The 8-bit write-only Control Register manages the operation of the RTI. Write to the Control Register by applying a logic zero to CS, CTRL, RD/WR, and ADDR IN (0); if ADDR IN (0) is a logic one a master reset occurs. Data is loaded into the Control Register via I/O pins DATA(7:0). Control Register writes must occur 50ns before the rising edge of COMSTR to latch data in the outgoing status word. Bit Initial Number Condition Description 0 1 2 3 [0] [0] [0] [0] Channel A Enable. A logic one enables Channel A biphase inputs. Channel B Enable. A logic one enables Channel B biphase inputs. Terminal Flag. A logic one sets the Terminal Flag bit of the Status Register. System Busy. A logic one sets the Busy bit of the System Register and inhibits RTI access to memory. No data words are retrieved or stored; command word is stored. Subsystem Busy. A logic one sets the Subsystem Flag bit of the Status Register. Self-Test Channel Select. This bit selects which channel the internal self-test checks; a logic one selects Channel A and a logic zero selects Channel B. Self-Test Enable. A logic one sets the RTI in the internal self-test mode and inhibits normal operation. Internal testing is not visible on biphase output channels. Service Request. A logic one sets the Service Request bit of the Status Register. 4 5 6 [0] [0] [0] 7 [0] CONTROL REGISTER (WRITE ONLY) X X X X X X X X SRV RQ [0] SELF TEST [0] SELF CH [0] SUBS [0] BUSY [0] TF [0] CH B EN [0] CH A EN [0] LSB MSB [ ] defines reset state Figure 4. Control Register System Register (Read Only) The 16-bit read-only System Register provides the RTI system status. Read the System Register by applying a logic zero to CS, CTRL, ADDR IN (0), and a logic one to RD/WR. The 16-bit contents of the System Register are read from data I/O pins DATA(15:0). Bit Initial Number Condition Description 0 1 2 3 4 5 [0] [0] [0] [0] [0] [0] MCSA(0). The LSB of the mode code or subaddress as indicated by the logic state of bit 5. MCSA(1). Mode code or subaddress as indicated by the state of bit 5. MCSA(2). Mode code or subaddress as indicated by the state of bit 5. MCSA(3). Mode code or subaddress as indicated by the state of bit 5. MCSA(4). Mode code or subaddress as indicated by the state of bit 5. MC/SA. A logic one indicates that bits 4 through 0 are the subaddress of the last command word, and that the last command word was a normal transmit orreceive command. A logic zero indicates that bits 4 through 0 are a mode code, and that the last command was a mode code. Channel A/B. A logic one indicates that the most recent command arrived onChannel A; a logic zero indicates that it arrived on Channel B. 6 [1] RTI-5 7 8 9 [0] [0] [1] Channel B Enabled. A logic one indicates that Channel B is available for both reception and transmission. Channel A Enabled. A logic one indicates that Channel A is available for both reception and transmission. Terminal Flag Enabled. A logic one indicates that the Bus Controller has not issued an Inhibit Terminal Flag mode code. A logic zero indicates that the Bus Controller, via the above mode code, is overriding the host system's ability to set the Terminal Flag bit of the status word. Busy. A logic one indicates the Busy bit is set. This bit is reset when the SystemBusy bit in the Control Register is reset. Self-Test. A logic one indicates that the RTI is in the self-test mode. This bit isreset when the self-test is terminated. TA Parity Error. A logic one indicates the wrong Terminal Address parity; it causes the biphase inputs to be disabled and a message error condition. This bit is reset by reloading the terminal address latch with correct parity. Message Error. A logic one indicates that a message error has occurred since the last System Register read. This bit is not reset until the System Register has been examined and the message error condition is removed. Valid Message. A logic one indicates that a valid message has been received since the last System Register read. This bit is not reset until the System Register has been examined. Terminal Active. A logic one indicates the device is executing a transmit or receive operation. The state of this bit is the logical NAND of the external XMIT and RCV pins. 10 11 12 [0] [0] [0] 13 [0] 14 [0] 15 [0] SYSTEM REGISTER (READ ONLY) TERM ACTV VAL MESS MESS ERR TAPA ERR SELFTEST BUSY TFEN CH A EN CH B EN CHNL A/B MC/ SA MCSA 4 MCSA 3 MCSA MCSA 2 1 MCSA 0 [0] MSB [0] [0] [0] [0] [0] [1] [0] [0] [1] [0] [0] [0] [0] [0] [0] LSB [ ] defines reset state Figure 5. System Registers RTI-6 Last Command Register (Read Only) The 16-bit read-only Last Command Register provides the host with last command and operational status information. The RTI transmits the lower 11 bits of this register along with terminal address upon receipt of a Transmit Last Command mode code. Read the Last Command Register by applying a logic zero to CS, CTRL, and a logic one to RD/WR and ADDR IN (0). The 16-bit contents of the Last Command Register are read from data I/O pins DATA(15:0). Bit Initial Number Condition Description 0 through 10 11 12 13 14 15 [all 1s] [0] [0] [1] [1] [1] Least significant 11 bits of the last command word. Busy Bit. System Register bit 10. Self-test. System Register bit 11. Terminal Flag Enabled. System Register bit 9. Channel A/B. System Register bit 6. Illegal Command. The RTI illegalized the last command. 1.3 Mode Codes and Subaddresses The UT1553B RTI provides subaddress and mode code decoding meeting MIL-STD-1553B. In addition, the device has automatic internal illegal command decoding for reserved MIL-STD-1553B mode codes. Upon command word validation and decode, status pins MCSA(4:0) and MC/SA become valid. Status pin MC/SA will indicate whether the data pins MCSA(4:0) are mode code or subaddress information. Status Register bits 5 through 0 contain the same information as pins MCSA(4:0) and MC/ SA. The system designer can use signals MCSA(4:0), MC/SA, BRDCST, XMIT, and RCV to illegalize mode codes, subaddresses, and other message formats via the Illegal Command (ILL COMM) input (see figure 23 on page 36). The RTI will internally decode the following mode codes as illegal: Mode codes which involve data transfer are processed like receive and transmit commands. The RTI will not generate DMA request for Transmit Status Word and Transmit Last Command mode codes since the information is stored internal to the RTI. The following mode codes require assistance from the host: - Synchronize - Initiate Self-Test - Reset Remote Terminal For example, the RTI will accept and respond to a Reset Remote Terminal mode code; however it will not perform a reset operation. The host must interpret the mode code and take appropriate action. The RTI does not define or interpret the following data words associated with mode code commands: - Dynamic Bus Control Selected Transmitter Shutdown Override Selected Transmitter Shutdown All Reserved Mode Codes - Transmit Vector Word - Synchronize With Data Word - Transmit Bit Word The RTI will accept and respond to mode code with data; the host must interpret or define the data word. The RTI will store or retrieve the data required for mode code command from block #1 of the receive or transmit page If the RTI receives one of the above mode codes, the RTI responds by transmitting a status word with the Message Error bit set to logic one. . RTI-7 RTI MODE CODE HANDLING PROCEDURE T/R 0 Mode Code 10100 Function Selected Transmitter Shutdown 2 Operation 1. 2. 3. 4. Command word stored MES ERR pin asserted Message error latch set in System Register Status word transmitted 0 10101 Override Selected Transmitter Shutdown 2 1. Command word stored 2. MES ERR pin asserted 3. Message error latch set in System Register 4. Status word transmitted 1. Command word stored 2. Data word stored 3. Status word transmitted 1. Command word stored 2. MES ERR pin asserted 3. Message error latch set in System Register 4. Status word transmitted 1. Command word stored 2. Status word transmitted 1. Command word stored 2. Status word transmitted 1. Command word stored 2. Status word transmitted 1. Command word stored 2. Alternate bus shutdown 3. Status word transmitted 1. Command word stored 2. Alternate bus enabled 3. Status word transmitted 1. Command word stored 2. Terminal Flag bit set to zero and disabled 3. Status word transmitted 1. Command word stored Bit 2. Terminal Flag bit enabled, but not set to logic one 3. Status word transmitted 1. Command word stored 2. Status word transmitted 1. Status word transmitted 2. Last command word transmitted 1. Command word stored 2. Status word transmitted 3. Data word transmitted 1. Command word stored 2. Status word transmitted 3. Data word transmitted 0 10001 Synchronize (w/data) 1 00000 Dynamic Bus Control 2 1 1 1 1 00001 00010 00011 00100 Synchronize 1 Transmit Status Word 3 Initiate Self-Test 1 Transmitter Shutdown 1 00101 Override Transmitter Shutdown 1 00110 Inhibit Terminal Flag Bit 1 00111 Override Inhibit Terminal Flag Bit 1 1 1 01000 10010 10000 Reset Remote Terminal 1 Transmit Last Command Word 3 Transmit Vector Word 1 10011 Transmit BIT Word Notes: 1. Further host interaction required for mode code operation. 2. Reserved mode code; A) MES ERR pin asserted, B) Message Error bit set, C) status word transmitted (ME bit set to logic one). 3.Status word not affected. RTI-8 1.4 MIL-STD-1553B Subaddress and Mode Code Definitions Subaddress Field Binary (Decimal) 00000 (00) 00001 (01) 00010 (02) 00011 (03) 00100 (04) 00101 (05) 00110 (06) 00111 (07) 01000 (08) 01001 (09) 01010 (10) 01011 (11) 01100 (12) 01101 (13) 01110 (14) 01111 (15) 10000 (16) 10001 (17) 10010 (18) 10011 (19) 10100 (20) 10101 (21) 10110 (22) 10111 (23) 11000 (24) 11001 (25) 11010 (26) 11011 (27) 11100 (28) 11101 (29) 11110 (30) 11111 (31) Table 1. Subaddress and Mode Code Definitions Per MIL-STD-1553B Message Format Receive Transmit Description 1 User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined 1 1 User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined 1 Mode Code Indicator Mode Code Indicator Note: 1. Refer to mode code assignments per MIL-STD-1553B 1.5 Remote Terminal Address Assign the RTI remote terminal address by either a software or hardware exercise. The host assigns the RTI remote terminal address by performing a Control Register write; the Terminal Address bus (TA(4:0)) is strobed into the RTI Remote Terminal Address Register upon completion of the Control Register write. To assign the RTI remote terminal address via hardware, use the TALEN/PARITY input pin operating in the terminal latch address enable mode. The Terminal Address bus is latched into the RTI while the TALEN is asserted (i.e., logic low). Valid remote terminal addresses (RTA) include decimal 0 through 31 if Broadcast is disabled, 0 through 30 if Broadcast is enabled Parity Checker An address parity check is performed to insure the remote terminal address applied to TA(4:0) was properly latched into the Remote Terminal Address Register. To perform a parity check, enable the RTI parity circuit via EXT TEST and EXT TST CH SEL A/B input pins. The parity bit is entered through the TALEN/PARITY input pin operating in the parity mode. Input pins EXT TEST and EXT TST CH SEL A/B control dual-function input pin TALEN/PARITY; see table 2 for description of operation. If a parity error exists, the Parity Error bit of the System Register is set to a logic one, biphase Channels A and B are disabled (set to logic zero), the Message Error bit set to logic one, and the message error pin is asserted. RTI-9 Table 2. Parity Checking STATE # EXT TEST 0 0 EXT TST CH SEL A/B 0 Function of TALEN/PARITY Terminal Address Latch Enable. Active low signal used to latch TA(4:0) into RTI. Internal parity checker disabled. Parity. Internal remote terminal address parity checker enabled. TALEN/PARITY pin functions as parity bit for TA(4:0) bus. Proper operation requires odd parity. Terminal Address Latch Enable. Do not assert EXT TST during reset, otherwise self-test is invoked. Terminal Address Latch Enable. Do not assert EXT TST during reset, otherwise self-test is invoked. 1 0 1 2 1 0 3 1 1 The following are examples of sequences used to enter remote terminal addresses into the RTI. Example 1. Hardware-Controlled Remote Terminal Address (parity check disabled): STATE 0, 2, or 3 (i.e., 00, 10, or 11) TALEN - asserted (i.e., logic low) TA(4:0) - valid RTA Example 2. Software-Controlled Remote Terminal Address (parity check disabled): EXT TEST and EXT TST CH SEL A/B in STATE 0, 2, or 3 (i.e., 00, 10, or 11) CTRL - logic zero CS - logic zero RD/WR - logic zero ADDR IN (0) - logic zero TALEN - logic one TA(4:0) - valid RTA Example 3. Software Controlled Remote Terminal Address (parity check enabled): EXT TEST and EXT TST CH SEL A/B in STATE 1 (i.e., 01) CTRL - logic zero CS - logic zero RD/WR - logic zero ADDR IN (0) - logic zero PARITY - input must provide odd parity for the TA(4:0) bus TA(4:0) - valid RTA For examples 1 and 2, enabling the parity check circuit (STATE 1) after the remote terminal address is stored results in a parity check of the data loaded into the Remote Terminal Address Register. 1.6 Internal Self-Test Setting bit 6 of the Control Register to a logic one enables the internal self-test. Disable Channels A and B at this time to prevent bus activity during self-test by setting bits 0 and 1 of the Control Register to a logic zero. Normal operation is inhibited when internal self-test is enabled. The RTI's self-test capability is based on the fact that the MIL-STD1553B status word sync pulse is identical to the command word sync pulse. Thus, if the status word from the encoder is fed back to the decoder, the RTI will recognize the incoming status word as a command word and thus cause the RTI to transmit another status word. After the host invokes self-test, the RTI self-test logic forces a status word transmission even though the RTI has not received a command word. The status word is sent to decoder A or B depending on the channel the host selected for self-test. The host controls the self-test by periodically changing the bit patterns in the status word being transmitted. Writing to the Control Register bits 2, 3, 4, and 8 changes the status word. Monitor the self-test by sampling either the System Register or the external status pins (i.e. Command Strobe (COMSTR), Transmit (XMIT), Receive (RCV)). For a more detailed explanation of internal self-test, consult the UTMC publication RTI Internal Self-Test Routine. 1.7 Power-up Master Reset Reset the RTI by invoking either a hardware or software master reset after power-up to place the device in a known state. The master reset clears the decoder and encoder registers, the command recognition logic, the control and error logic (which includes the Status, Control and System Registers), the data transfer logic, and the memory address control logic. After reset, configure the device for operation via a Control Register write. RTI-10 Perform a hardware reset by asserting the MRST input pin for a minimum of 500ns. During reset negate the EXT TEST pin (i.e., logic low); assertion of the EXT TEST pin forces the RTI to enter the external self-test mode of operation. Software reset the RTI by simultaneously applying a logic zero to input pins CS, RD/WR, and CTRL while the least significant bit of the address input bus is a logic one (ADDR IN (0)=0). word, sets the Message Error output, and sets the message error latch in the System Register. Use the following RTI outputs to externally decode an illegal command, Mode Code or Subaddress indicator (MC/ SA), Mode Code or Subaddress bus MCSA(4:0), Command Strobe (COMSTR), Broadcast (BRDCST), etc. (See figure 6 pages 11-12). To illegalize a transmit command the ILL COMM pin is asserted 3.3ms after STATUS goes to a logic one. Assertion of the ILL COMM pin within 3.3ms allows the RTI to respond with the Message Error bit of the outgoing status word at a logic one. For an illegal receive command, the ILL COMM pin is asserted within 18.2ms after the COMSTR transitions to a logic zero in order to suppress data words from being stored (suppress DMARQ assertions). In addition, the ILL COMM pin must be at a logic one throughout the reception of the message until STATUS is asserted. If the illegal command is mode code 2, 4, 5, 6, 7, or 18, assert the ILL COMM pin within 664ns after Command Strobe (COMSTR) transitions to logic zero. Asserting the ILL COMM pin within the 664 nanoseconds inhibits the mode code function. The above timing conditions also apply when the host externally decodes an illegal broadcast command. The host must remove the illegal command condition so that the next command is not falsely decoded as illegal. These requirements are easily met if the COMSTR output is used to qualify the ILL COMM input to the RTI. 1.8 Encoder and Decoder The RTI interfaces directly to a bus transmitter/receiver via the RTI Manchester II encoder/decoder. The UT1553B RTI receives the command word from the MIL-STD-1553B bus and processes it either by the primary or secondary decoder. Each decode checks for the proper sync pulse and Manchester waveform, edge skew, correct number of bits, and parity. If the command is a receive command, the RTI processes each incoming data word for correct word count and contiguous data. If an invalid message error is detected, the message error pin is asserted, the RTI ceases processing the remainder (if any) of the message, and it then suppresses status word transmission. Upon command validation recognition, the external status outputs are enabled. Reception of illegal commands does not suppress status word transmission. A timer precludes transmission greater than 730ms by the assertion of fail-safe timer (TIMERON). This timer is reset upon receipt of another valid command. 1.9 Illegal Command Decoding The host has the option of asserting the ILL COMM pin to illegalize a received command word. On receipt of an illegal command, the RTI sets the message error bit in the status BIPHASE IN COMSTR RCV CS COMMAND WORD P DS DATA WORD P DS DATA WORD P 18.2s ILL COMM DMA Activity Suppressed STATUS BIPHASE OUT SS STATUS WORD P Note: 1. Illegal command condition; status word Message Error bit set to logic one, RTIMES ERR pin set to a logic one, RTI Status Register Message Error bit set to logic one. Figure 6a. Illegal Receive Command Decoding RTI-11 BIPHASE IN COMSTR CS COMMAND WORD P XMIT ILL COMM 3.3s 1.0s (min) DMA Activity Suppressed STATUS BIPHASE OUT SS STATUS WORD P Note: 1. Illegal command condition; status word Message Error bit set to logic one, RTI MES ERR pin set to a logic one, RTI Status Register Message Error bit set to logic one. Figure 6b. Illegal Transmit Command Decoding CS COMMAND WORD P BIPHASE IN COMSTR MC/SA 664ns ILL COMM Note: 1. To illegalize mode codes 2, 4, 5, 6, 7, or 18 assert ILL COMM within 664ns of COMSTR's transition to logic zero. Asserting the ILL COMM within 664ns inhibits the mode code function. Figure 6c. Mode Code Command Decoding 2.0 MEMORY MAP EXAMPLE The RTI is capable of addressing 2048 x 16 of external memory for message storage. The 2K memory space is divided into two 1K pages and subdivided into 32 blocks of 32 x 16: Page 1 (Receive): 32 blocks for receive messages (32 x 16) Page 2 (Transmit): 32 blocks for transmit messages (32 x 16) The T/R bit of the command word becomes the most significant bit of the data pointer; the T/R bit serves to divide the RAM into transmit and receive pages of 1K each. The 5-bit subaddress/mode field is used to select 1 of 32 possible message storage blocks within the transmit or receive message page. The 5-bit word count/mode code field acts as a data pointer to select one of 32 locations within the message storage block. Multiple word messages are stored from top to bottom within the message storage block. For mode commands, the address data pointer always contains 00000 in the MC/SA field, regardless of whether 00000 or 11111 was received. Forcing the mode code field to 00000 reserves the first message storage block on both pages (receive and transmit) for mode code messages that require data. The 5-bit mode code specifies which of the 32 locations within the message storage block to access. Address Decode The RTI derives addresses (i.e., data pointers) for external memory directly from the 11 least significant bits of the command word. The address data pointer corresponds to ADDR OUT (10:0) during RTI memory accesses. T/R = ADDR OUT (10) SUBADDRESS/MODE = ADDR OUT (9:5) WORD COUNT/MODE CODE = ADDR OUT (4:0) RTI-12 For "wrap-around" applications (transmission of data previously received), force the RTI to store and receive messages on one memory page. To accomplish one-page operation do not use the T/R output pin. Eliminating the T/ R limits the RTI access to only one page and the RTI will not differentiate between receive and transmit pages. Table 3. RTI Memory Map 1: Receive Memory Map Block # 2: Transmit Memory map Address Field (hex) 000 to 01F 020 to 03F Block # 1 2 Operation Mode Code 1 Subaddress 1 Address Field (hex) 400 to 41F 420 to 43F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Operation Mode Code 1 Subaddress 1 Subaddress 2 Subaddress 3 Subaddress 4 Subaddress 5 Subaddress 6 Subaddress 7 Subaddress 8 Subaddress 9 Subaddress 10 Subaddress 11 Subaddress 12 Subaddress 13 Subaddress 14 Subaddress 15 Subaddress 16 Subaddress 17 Subaddress 18 Subaddress 19 Subaddress 20 Subaddress 21 Subaddress 22 Subaddress 23 Subaddress 24 Subaddress 25 Subaddress 26 Subaddress 27 Subaddress 28 Subaddress 29 Subaddress 30 Unused 040 to 05F 060 to 07F 080 to 09F 0A0 to 0BF 0C0 to 0DF 0E0 to 0FF 100 to 11F 120 to 13F 140 to 15F 160 to 17F 180 to 19F 1A0 to 1BF 1C0 to 1DF 1E0 to 1FF 200 to 21F 220 to 23F 240 to 25F 260 to 27F 280 to 29F 2A0 to 2BF 2C0 to 2DF 2E0 to 2FF 300 to 31F 320 to 33F 340 to 35F 360 to 37F 380 to 39F 3A0 to 3BF 3C0 to 3DF 3E0 to 3FF 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Subaddress 2 Subaddress 3 Subaddress 4 Subaddress 5 Subaddress 6 Subaddress 7 Subaddress 8 Subaddress 9 Subaddress 10 Subaddress 11 Subaddress 12 Subaddress 13 Subaddress 14 Subaddress 15 Subaddress 16 Subaddress 17 Subaddress 18 Subaddress 19 Subaddress 20 Subaddress 21 Subaddress 22 Subaddress 23 Subaddress 24 Subaddress 25 Subaddress 26 Subaddress 27 Subaddress 28 Subaddress 29 Subaddress 30 Unused 440 to 45F 460 to 47F 480 to 49F 4A0 to 4BF 4C0 to 4DF 4E0 to 4FF 500 to 51F 520 to 53F 540 to 55F 560 to 57F 580 to 59F 5A0 to 5BF 5C0 to 5DF 5E0 to 5FF 600 to 61F 620 to 63F 640 to 65F 660 to 67F 680 to 69F 6A0 to 6BF 6C0 to 6DF 6E0 to 6FF 700 to 71F 720 to 73F 740 to 75F 760 to 77F 780 to 79F 7A0 to 7BF 7C0 to 7DF 7E0 to 7FF Notes: 1. Receive mode codes with data: - Synchronize with data - Selected Transmitter Shutdown (Illegal) - Override Selected Transmitter Shutdown (Illegal) 2. Transmit mode codes with data: - Transmit Vector Word - Transmit Bit Word RTI-13 3.0 PIN IDENTIFICATION AND DESCRIPTION BIPHASE OUT BIPHASE OUT A O BIPHASE OUT A Z BIPHASE OUT B O BIPHASE OUT B Z 27 (L8) 28 (K8) 32 (L11) 30 (L10) 37 (H10) 39 (G9) 33 (K10) 34 (J10) BIPHASE IN BIPHASE IN A O BIPHASE IN A Z BIPHASE IN B O BIPHASE IN B Z (K3) 13 (K1) 9 (H2) 7 (G3) 5 (G1) 3 (F3) 1 (E1) 8 (F2) 8 (D2) 7 (B1) 7 (B2) 7 (A1) (B3) (A2) (A3) (B4) (A4) (C5) (B5) (A5) (A6) (C7) (B6) (A8) (A9) (A10) (A11) 74 73 72 71 70 69 68 67 66 65 63 61 59 57 55 53 ADDR IN 0 ADDR IN 1 ADDR IN 2 ADDR IN 3 ADDR IN 4 ADDR IN 5 ADDR IN 6 ADDR IN 7 ADDR IN 8 ADDR IN 9 ADDR IN 10 DATA I/O 0 DATA I/O 1 DATA I/O 2 DATA I/O 3 DATA I/O 4 DATA I/O 5 DATA I/O 6 DATA I/O 7 DATA I/O 8 DATA I/O 9 DATA I/O 10 DATA I/O 11 DATA I/O 12 DATA I/O 13 DATA I/O 14 DATA I/O 15 ADDRESS BUS ADDR IN(10:0) DATA BUS DATA(15:0) TERMINAL ADDRESS TA0 TA1 TA2 TA3 TA4 TALEN/PARITY 64 (C6) 62 (A7) 60 (B7) 58 (B8) 56 (B9) 52 (C10) 14 (L2) 16 (K4) 17 (L4) 18 (J5) 19 (K5) MODE/CODE SUBADDRESS MCSA0 MCSA1 MCSA2 MCSA3 MCSA4 UT1553B RTI STATUS SIGNALS MES ERR TIMERON COMSTR MC/SA RCV XMIT RRD/RWR RCS STATUS CH A/B BRDCST 49 (D10) 41 (G11) 22 (J6) 21 (K6) 51 (B11) 38 (H11) 45 (E11) 43 (F9) 23 (J7) 26 (L6) 36 (J11) 25 (K7) 44 (E9) 46 (E10) 50 (C11) 15 (L3) 20 (L5) (L1) (J2) (J1) (H1) (G2) (F1) (E3) (E2) (D1) (C1) (C2) 11 10 8 6 4 2 84 82 80 78 76 ADDR OUT 0 ADDR OUT 1 ADDR OUT 2 ADDR OUT 3 ADDR OUT 4 ADDR OUT 5 ADDR OUT 6 ADDR OUT 7 ADDR OUT 8 ADDR OUT 9 ADDR OUT 10 ADDRESS BUS ADDR OUT (10:0) (L9) 29 (K9) 31 (D11) 48 (F11) 47 EXT TEST TEST EXT TST CH SEL A/B MEMCK DMARQ DMA CONTROL SIGNALS BCEN CS RD/WR CTRL ADOEN ILL COMM (B10) 54 (K2) 12 (F10) 42 (K11) 35 (L7) 24 (G10) 40 VDD VSS VSS 12MHz 2MHz MRST POWER GROUND CLOCK RESET Note: Pingrid array numbers are in parentheses. LCC pin numbers are not in parentheses. Figure 7. UT1553B RTI Pin Description RTI-14 Legend for TYPE and ACTIVE fields: TI = TTL input TUI = TTL input (pull-up) TDI = TTL input (pull-down) TO = TTL output TTO = Three-state TTL output TTB = Three-state TTL bidirectional [ ] - Values in parentheses indicate the initialized state of output pin. DATA BUS NAME DATA I/O 15 DATA I/O 14 DATA I/O 13 DATA I/O 12 DATA I/O 11 DATA I/O 10 DATA I/O 9 DATA I/O 8 DATA I/O 7 DATA I/O 6 DATA I/O 5 DATA I/O 4 DATA I/O 3 DATA I/O 2 DATA I/O 1 DATA I/O 0 PIN NUMBER LCC PGA 53 55 57 59 61 63 65 66 67 68 69 70 71 72 73 74 A11 A10 A9 A8 B6 C7 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1 TYPE TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB ACTIVE DESCRIPTION ----------------Bit 15 (MSB) of the bidirectional Data bus. Bit 14 of the bidirectional Data bus. Bit 13 of the bidirectional Data bus. Bit 12 of the bidirectional Data bus. Bit 11 of the bidirectional Data bus. Bit 10 of the bidirectional Data bus. Bit 9 of the bidirectional Data bus. Bit 8 of the bidirectional Data bus. Bit 7 of the bidirectional Data bus. Bit 6 of the bidirectional Data bus. Bit 5 of the bidirectional Data bus. Bit 4 of the bidirectional Data bus. Bit 3 of the bidirectional Data bus. Bit 2 of the bidirectional Data bus. Bit 1 of the bidirectional Data bus. Bit 0 (LSB) of the bidirectional Data bus. INPUT ADDRESS BUS NAME ADDR IN 10 ADDR IN 9 ADDR IN 8 ADDR IN 7 ADDR IN 6 ADDR IN 5 ADDR IN 4 ADDR IN 3 ADDR IN 2 ADDR IN 1 ADDR IN 0 PIN NUMBER LCC PGA 75 B2 77 79 81 83 1 3 5 7 9 13 B1 D2 F2 E1 F3 G1 G3 H2 K1 K3 TYPE TI TI TI TI TI TI TI TI TI TI TI ACTIVE DESCRIPTION -----------Bit 10 (MSB) of the Address Input bus. Bit 9 of the Address Input bus. Bit 8 of the Address Input bus. Bit 7 of the Address Input bus. Bit 6 of the Address Input bus. Bit 5 of the Address Input bus. Bit 4 of the Address Input bus. Bit 3 of the Address Input bus. Bit 2 of the Address Input bus. Bit 1 of the Address Input bus. Bit 0 (LSB) of the Address Input bus. RTI-15 OUTPUT ADDRESS BUS NAME ADDR OUT 10 ADDR OUT 9 ADDR OUT 8 ADDR OUT 7 ADDR OUT 6 ADDR OUT 5 ADDR OUT 4 ADDR OUT 3 ADDR OUT 2 ADDR OUT 1 ADDR OUT 0 PIN NUMBER LCC PGA 76 C2 78 80 82 84 2 4 6 8 10 11 C1 D1 E2 E3 F1 G2 H1 J1 J2 L1 TYPE TTO TTO TTO TTO TTO TTO TTO TTO TTO TTO TTO ACTIVE DESCRIPTION -----------Bit 10 (MSB) of the Address Output bus. Bit 9 of the Address Output bus. Bit 8 of the Address Output bus. Bit 7 of the Address Output bus. Bit 6 of the Address Output bus. Bit 5 of the Address Output bus. Bit 4 of the Address Output bus. Bit 3 of the Address Output bus. Bit 2 of the Address Output bus. Bit 1 of the Address Output bus. Bit 0 (LSB) of the Address Output bus. REMOTE TERMINAL ADDRESS INPUTS NAME TA4 TA3 TA2 TA1 TA0 TALEN/PARITY PIN NUMBER LCC PGA 56 B9 58 60 62 C6 52 B8 B7 A7 64 C10 TYPE TUI TUI TUI TUI TUI TUI ACTIVE DESCRIPTION ------Remote Terminal Address bit 4 (MSB). Remote Terminal Address bit 3. Remote Terminal Address bit 2. Remote Terminal Address bit 1. Remote Terminal Address bit 0. Remote Terminal Address Latch Enable/ Remote Terminal Parity Input. Function of input is defined by he state of pin EXT TEST and EXT TST CH SEL A/B. For EXT TEST = 0, EXT TST CH SEL A/B = 1, TALEN/PARITY must provide odd parity for the Remote Terminal Address. For all other states of EXT TEST and EXT TST CH SEL A/B (i.e., 00, 10, 11) TALEN/PARITY functions as an active low address strobe. ; RTI-16 MODE CODE/SUBADDRESS OUTPUTS NAME MC/SA PIN NUMBER LCC PGA 21 K6 TYPE ACTIVE DESCRIPTION TO -- Mode Code/Subaddress Indicator. If MC/SA is low, it indicates that the most recent command word is a mode code command. If MC/SA is high, it indicates that the most recent command word is for a subaddress. This output indicates whether the mode code/subaddress outputs (i.e., MCSA(4:0)) contain mode code or subaddress information. Mode Code/Subaddress 4. If MC/SA is low, this pin represents the most significant bit of the the most recent command word (the MSB of the mode code). If MC/SA is high, this pin represents the MSB of the subaddress. Mode Code/Subaddress 3. Mode Code/Subaddress 2. Mode Code/Subaddress 1. Mode Code/Subaddress 0. If MC/SA is low, this pin represents the least significant bit of the the most recent command word. If MC/SA is high, this pin represents the LSB of the subaddress MCSA4 19 K5 TO -- MCSA3 18 MCSA2 17 MCSA1 16 MCSA0 14 J5 L4 K4 L2 TO TO TO TO ----- BIPHASE INPUTS NAME BIPHASE IN A Z BIPHASE IN A O BIPHASE IN B Z BIPHASE IN B O PIN NUMBER LCC PGA 39 G9 37 34 33 H10 J10 K10 DESCRIPTION TI TI TI TI ----Receiver - Channel A, Zero Input. Idle low Manchester input from the 1553 bus transceiver. Receiver - Channel A, One Input. This input is thecomplement of BIPHASE IN A Z. Receiver - Channel B, Zero Input. Idle low Manchester input from the 1553 bus transceiver. Receiver - Channel B, One Input. This input is the complement of BIPHASE IN B Z. RTI-17 BIPHASE OUTPUTS NAME BIPHASE OUT A Z PIN NUMBER LCC PGA 28 K8 TYPE TO ACTIVE -DESCRIPTION Transmitter - Channel A, Zero Output. This Manchester-encoded data output is connected to the 1553 bus transmitter input. The output is idle low. Transmitter - Channel A, One Output. This output is the complement of BIPHASE OUT A Z. The output is idle low. Transmitter - Channel B, Zero Output. This Manchester-encoded data output is connected to the 1553 bus transmitter. The output is idle low. Transmitter - Channel B, One Output. This output is the complement of BIPHASE OUT B Z. The output is idle low. BIPHASE OUT A O 27 L8 TO -- BIPHASE OUT B Z 30 L10 TO -- BIPHASE OUT B O 32 L11 TO -- MASTER RESET AND CLOCK NAME MRST PIN NUMBER LCC PGA 40 G10 TYPE TUI ACTIVE AL DESCRIPTION Master Reset. Initializes all internal functions of the RTI. MRST must be asserted 500 nanoseconds before normal RTI operation. (500ns minimum). 12MHz Input Clock. This is the RTI system clock that requires an accuracy greater than 0.01% with a duty cycle from 50% 10%. 2MHz Clock Output. This is a 2MHz output generated by the 12MHz input clock. This clock is stopped when MRST is low. 12MHz 35 K11 TI -- 2MHz 24 L7 TO -- POWER AND GROUND NAME VDD VSS PIN NUMBER LCC PGA 54 B10 12 42 K2 F10 TYPE PWR GND GND ACTIVE ---DESCRIPTION +5VDC. Power supply must be +5VDC 10%. Ground reference. Zero VDC logic ground. RTI-18 CONTROL PINS NAME CS PIN NUMBER LCC PGA 44 E9 TYPE TI ACTIVE DESCRIPTION AL Chip Select. Active low input for host access of transparent memory or the RTI internal registers. In the transparent memory configuration CS is propagated through the RTI to the RCS output. Control. The host processor uses the active low CTRL input signal in conjunction with CS and RD/ WR to access the RTI internal registers. CTRL is also used in the software assignment of the terminal address and programmed reset. Address Output Enable. When ADOEN is low the Address Out bus (ADDR OUT (15:0)) is active. If ADOEN = 1 the Address Out bus is high impedance. Read/Write. The host processor uses a high level on this input in conjunction with CS and CTRL to read the RTI internal registers. A low level on this input is used in conjunction with CS and CTRL to write to internal RTI registers. In the transparent memory configuration RD/WR is propagated through the RTI to the RRD/RWR output. Broadcast Enable. Active low input enables broadcast commands. Illegal Command. The host processor uses the ILL COMM input to inform the RTI that the present command is illegal. ILL COMM is used in conjunction with MCSA(4:0) and MC/SA to define system dependent illegal commands. CTRL 50 C11 TI AL ADOEN 15 L3 TI AL RD/WR 46 E10 TI -- BCEN ILL COMM 25 20 K7 L5 TUI TDI AL AH RTI-19 STATUS OUTPUTS NAME RCS RRD/RWR PIN NUMBER LCC PGA 43 45 F9 E11 TYPE TO TO ACTIVE DESCRIPTION AL -RAM Chip Select. Active low output used to enable memory for access. RAM Read/Write. High output enables memory read, low output enables memory write, used in conjunction with RCS). Normally high output. Command Strobe. COMSTR is an active low output of 500ns duration identifying receipt of a valid command. Fail-safe Timer. The TIMERON output pulses low for 730ms when the RTI begins transmitting (i.e., rising edge of STATUS) to provide a fail-safe timer meeting the requirements of MIL-STD-1553B. This pulse is reset when COMSTR goes low or during Master Reset. in the external self-test mode TIMERON does not recognize COMSTR and resets after 730ms. Message Error. The active high MES ERR output signals that the Message Error bit in the Status Register has been set due to receipt of an invalid command or an error during message sequence. MES ERR will reset to logic zero on receipt of next valid command. Channel A/B. Output identifying the channel on which the most recent valid command was received. Channel A = 1, Channel B = 0. Transmit. Active low output identifies a transmit command message transfer by the RTI is in progress. Receive. Active low output identifies a receive command message transfer by the RTI is in progress. Broadcast. BRDCST is an active low output that identifies receipt of a valid broadcast command. Status. Active high output pulse indicating that the RTI is in the process of transmitting a status word. COMSTR 22 J6 TO AL TIMERON 41 G11 TO AL MES ERR 49 D10 TO AH CH A/B 26 L6 TO -- XMIT 38 H11 TO AL RCV 51 B11 TO AL BRDCST 36 J11 TO AL STATUS 23 J7 TO AH RTI-20 BUS ARBITRATION NAME DMARQ MEMCK PIN NUMBER LCC PGA 47 F11 48 D11 TYPE TO TI ACTIVE DESCRIPTION AH AL Direct Memory Access Request. Active high output requesting RTI access to memory. Memory Clock (DMA Grant). Active low input signaling the RTI that a memory access is granted. Internal to the RTI, receipt of MEMCK generates RAM chip select and RAM read/write signals. External Self-test Enable. Multi-function input pin. In self-test mode forcing this pin high allows the monitoring of self-test activity at the bus stub. When the RTI is not in self-test this pin defines the function of TALEN/PARITY. External Self-test Channel Select. A/B Multifunction input pin. In self-test mode forcing this pin high selects the channel on which the selftest is performed (Channel A = 1, Channel B = 0). When the RTI is not in self-test this pin defines the function of TALEN/PARITY. EXT TST 29 L9 TDI -- EXT TST CH SEL A/B 31 K9 TUI -- 4.0 OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS (referenced to VSS) SYMBOL VDD VIO II TSTG PD TJ JC DC supply voltage Voltage on any pin DC input current Storage temperature Maximum power dissipation Maximum junction temperature Thermal resistance, junction-to-case 1 PARAMETER LIMITS -0.3 to +7.0 -0.3 to VDD+0.3 10 -65 to +150 300 +175 20 UNIT V V mA C mW C C/W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions SYMBOL PARAMETER LIMITS UNIT VDD VIN TC FO DC supply voltage DC input voltage Temperature range Operating frequency 4.5 to 5.5 0 to VDD -55 to +125 12 .01% V V C MHz RTI-21 5.0 DC ELECTRICAL CHARACTERISTICS (VDD = 5.0V 10%; -55C < TC < +125C) SYMBOL VIL PARAMETER Low-level input voltage CONDITION MINIMUM MAXIMUM 0.8 UNIT V VIH IIN High-level input voltage Input leakage current TTL inputs Inputs with pull-down resistors Inputs with pull-up resistors Low-level output voltage High-level output voltage Three-state output leakage current Short-circuit output current 1, 2 Input capacitance 3 Output capacitance 3 Bidirect I/O capacitance 3 Average operating current 1, 4 Quiescent current VIN = VDD or VSS VIN = VDD VIN = VSS IOL = 4mA IOH = -400A VO = VDD or VSS 2.0 -10 110 -2750 2.4 -10 +10 10 2750 -110 0.4 V A A A V V A VOL VOH IOZ IOS CIN COUT CIO IDD QIDD VDD = 5.5V, VO = VDD VDD = 5.5V, VO = 0V = 1MHz @ 0V = 1MHz @ 0V = 1MHz @ 0V = 12MHz, CL = 50pF Note 5 90 -90 10 15 25 50 1.5 mA mA pF pF pF mA mA Notes: 1. Supplied as a design limit but not guaranteed or tested. 2. Not more than one output may be shorted at a time for a maximum duration of one second. 3. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance. 4. Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching. Voltage supply should be adequately sized and decoupled to handle a large surge current. 5. All inputs with internal pull-ups or pull-downs should be left open circuit. All other inputs tied high or low. BIT TIMES COMMAND WORD 123 45678 5 9 1 T/R 10 11 12 13 14 5 SUBADDRESS/MODE CODE 15 16 17 18 19 5 DATA WORD COUNT/ MODE CODE 20 1 P SYNC REMOTE TERMINAL ADDRESS DATA WORD SYNC STATUS WORD SYNC 5 REMOTE TERMINAL ADDRESS 16 DATA 1 MESSAGE ERROR 1 P 1 INSTRUMENTATION 1 SERVICE REQUEST RESERVED 1 BROADCAST COMMAND RECEIVED 1 BUSY 1 SUBSYSTEM FLAG 1 DYNAMIC BUS CONTROL ACCEPTANCE 1 TERMINAL FLAG 1 PARITY Figure 8. MIL-STD-1553B Word Formats RTI-22 6.0 AC ELECTRICAL CHARACTERISTICS (Over recommended operating conditions) VIH MIN VIL MAX 1 ta 3, 4 INPUT 2 tb 1 1 2 td 2 te VIH MIN VIL MAX VOH MIN VOL MAX VOH MIN VOL MAX VOH MIN VOL MAX tf IN-PHASE OUTPUT OUT-OF-PHASE OUTPUT tc BUS tg th SYMBOL ta tb tc td te tf tg th PARAMETER INPUT to response INPUT INPUT INPUT INPUT INPUT INPUT INPUT to response to response to response to data valid to high Z to high Z to data valid Notes: 1. Timing measurements made at (VIH MIN + VIL MAX)/2. 2. Timing measurements made at (VOL MAX + VOH MIN)/2. 3. Based on 50pF load. Figure 9a. Typical Timing Measurements 5V IREF (source) 90% 50pF VREF 10% 0V IREF (sink) Note: 30pF including scope probe and test socket 3V 90% 10% < 2ns Input Pulses < 2ns Figure 9b. AC Test Loads and Input Waveforms RTI-23 t10a DMARQ t10b t10e MEMCK t10d RCS t10c t10i RRD/RWR t10h t10f DATA BUS t10g ADDR OUT BUS Figure 10. RTI Memory Write SYMBOL t10a t10b t10c t10d t10e t10f t10g t10h t10i PARAMETER ADDR OUT valid to DMARQ active 3 DMARQ active to MEMCK active 2, 3 MEMCK active to RCS active 4 MEMCK inactive to RCS inactive 4 MEMCK pulse width 1, 2, 4 MEMCK active to DATA bus valid 4 MEMCK inactive to DATA bus high impedance 3 MEMCK active to RRD/RWR active MEMCK inactive to RRD/RWR inactive MINIMUM 883 0 83 5 - MAXIMUM 992 67 61 115 101 61 58 UNITS ns ns ns ns ns ns ns ns ns Notes: 1. Allows a 20ns data valid set-up time before RCS and RRD/RWR go high. 2. The sum tb + te must not exceed 18.8ms. 3. Supplied as a design limit, but not guaranteed or tested. 4. Guaranteed by test. RTI-24 t11a DMARQ t11h t11b t11e MEMCK t11d RCS t11c t11f DATA BUS t11g ADDR OUT BUS Figure 11. RTI Memory Read SYMBOL t11a t11b t11c t11d t11e t11f t11g t11h PARAMETER ADDR OUT valid to DMARQ active 3 DMARQ active to MEMCK active 3 MEMCK active to RCS active 4 MEMCK inactive to RCS inactive 4 MEMCK pulse width 1, 2, 4 Input DATA valid to MEMCK inactive 4 Input DATA valid after RCS inactive 4 DMARQ active to MEMCK inactive 4 MINIMUM 883 0 50 45 5 MAXIMUM 992 14.9 67 61 - UNITS ns s ns ns ns ns ns s - 18.3 Notes: 1. Allows a 20ns data valid set-up time before RCS and RRD/RWR go high. 2. The sum tb + te must not exceed 18.8ms. 3. Supplied as a design limit, but not guaranteed or tested. 4. Guaranteed by test. RTI-25 ADDR IN (0) t12c WRITE CONTROL (CNTRL + CS + RD/WR) Logical OR t12a DATA BUS t12d t12b Figure 12. Control Register Write Timing SYMBOL t12a t12b t12c PARAMETER Input DATA valid before WRITE 3 CONTROL inactive (set-up time) Input DATA valid after WRITE 3 CONTROL inactive (hold-time) ADDR IN1, 3 valid before WRITE CONTROL asserts ADDR IN 2, 3 after WRITE CONTROL valid negates MINIMUM 20 MAXIMUM - UNITS ns 25 - ns 20 - ns t12d 20 - ns Notes: 1. Set-up time required to prevent inadvertent software reset. 2. Hold-time required to prevent inadvertent software reset. 3. Guaranteed by test. RTI-26 ADDR IN (0) READ CONTROL (CNTRL + CS ) Logical OR 1, 2 t13b DATA BUS t13a t13c Figure 13. System and Last Command Register Read Timing SYMBOL PARAMETER MINIMUM MAXIMUM UNITS t13a t13b t13c DATA bus valid after READ CONTROL valid whilve ADDR IN (0) = 0 or 1 DATA bus valid after ADDR IN (0) = 0 or 1 while READ CONTROL = 0 READ CONTROL 3 negation to DATA bus high impedance - 132 ns - 70 ns - 101 ns Notes: 1. ADDR IN (0) = 0 System Register read. 2. ADDR IN (0) = 1 Last Command Register read. 3. Supplied as a design limit but not guaranteed or tested. RTI-27 TIMERON t14a t14c STATUS t14b BIPHASE OUT t14d COMSTR Figure 14. RT Fail-Safe Timer Signal Relationships SYMBOL t14a PARAMETER STATUS active to TIMERON active 1 TIMERON active to first BIPHASE OUT transition 1 TIMERON low pulse width 1 COMSTR active to TIMERON reset 1 MINIMUM 4 MAXIMUM 31 - UNITS ns t14b t14c t14d 1.2 ms - 732 ms 31 ns Note: 1. Supplied as a design limit, but not guaranteed or tested. RTI-28 CS t15b RCS t15a RD/WR t15c RRD/RWR t15dv ADDR IN BUS t15e ADDR OUT BUS t15g ADOEN t15i MEMCK Figure 15. RTI Propagation Delays t15j t15h t15f SYMt15a t15b t15c t15d t15e t15f t15g t15h t15i t15j PARAMETER MINIMUM 2 2 MAXIMUM 48 40 45 35 52 44 42 50 - UNITS ns ns ns ns ns ns ns ns ns ns CS active to RCS active 2 CS negation to RCS negation 6 2 RD/WR active to RRD/RWR active RD/WR negation to RRD/RWR negation 2 CS active to ADDR OUT valid 2 ADDR IN valid to ADDR OUT valid 6 13 10 ADOEN negation to ADDR OUT high impedance 1 ADOEN active to ADDR OUT active 2 CS active to MEMCK active (MEMCK not recognized) 1 CS negation to MEMCK active (MEMCK recognized) 1 Note: 1. Supplied as a design limit, but not guaranteed or tested. 2. Guaranteed by test. RTI-29 3 BIPHASE IN COMMAND P t16a t16b COMSTR RCV XMIT t16c CH A/B BRDCST MC/SA MCSA(4:0) ADDR OUT 1 MESS ERR Figure 16. Command Word Validation t16d t16e SYMBOL PARAMETER MINIMUM MAXIMUM UNITS t16a t16b t16c t16d t16e Command word parity to COMSTR and RCV or XMIT active 4 COMSTR pulse width 4 Command word parity to CH A/B valid 4 Status output signals valid to COMSTR active 2, 4 MES ERR reset after COMSTR active 4 3.58 3.67 502 2.66 - s ns s ns 499 2.58 430 745 750 ns Notes: 1. ADOEN is asserted (i.e., logic low). 2. Status signals include BRDCST, MC/SA, MCSA(4:0), and ADDR OUT. 3. Measured from mid-bit parity crossing. 4. Supplied as a design limit, but not guaranteed or tested. RTI-30 1 BIPHASE IN DATA P t17a SYNC t17b 2 STATUS BIPHASE OUT P DMARQ t17d t17c STATUS RCV t17e ADDR OUT Figure 17. Receive Command Message Processing SYMBOL PARAMETER MINIMUM MAXIMUM UNITS t17a t17b t17c t17d t17e Data word 1, 3 parity bit to status word response Data word parity bit to DMARQ active 2, 3 STATUS active to BIPHASE OUT active 3 STATUS pulse width 3 ADDR OUT valid before DMARQ (H) 3 8.80 9.37 s s s s s 3.58 1.24 4.48 0.90 3.68 1.25 4.98 - Notes: 1. Measured from last data word mid-bit parity crossing. 2. Measured from transmitted status word sync field mid-bit crossing. 3. Supplied as a design limit, but not guaranteed or tested. RTI-31 BIPHASE 20 0 20 0 t18a DMARQ t18b t18c XMIT Figure 18. Transmitted Data Timing SYM* t18a * t18b * t18c PARAMETER MINIMUM 17.15 460 MAXIMUM UNITS DMARQ active to sync field of transmitted data word DMARQ active to DMARQ active XMIT negation after last DMARQ active 17.18 19.2 500 s s s Note: * Supplied as a design limit but not guaranteed or tested. RTI-32 1 BIPHASE IN BIPHASE COMSTR t19c STATUS t19e XMIT t19g t19d t19f DATA/CMD P t19a t19b SYNC 2 STATUS P MES ERR Figure 19. Mode Command Message Processing SYMBOL PARAMETER MINIMUM MAXIMUM UNITS * t19a *t 19b *t 19c *t 19d *t 19e *t 19f *t 19g Response time BIPHASE IN to BIPHASE OUT 2 Command word parity bit to COMSTR assertion 1 STATUS active to BIPHASE OUT active STATUS pulse width Command word parity bit to XMIT assertion XMIT pulse width for mode code reception Command word parity bit to MES ERR assertion 3.58 8.80 1.24 4.48 3.58 1.00 6.57 3.67 9.37 1.25 4.98 3.67 6.68 s s s s s s s Notes: 1. Measured from data or command word mid-bit parity crossing. 2. Measured from transmitted status word sync field mid-bit crossing. * Supplied as a design limit but not guaranteed or tested. RTI-33 1 BIPHASE IN MES ERR DATA P t20a 1 BIPHASE IN MES ERR Figure 20. Message Error RCV CMD P XMIT CMD P t20b SYMBOL PARAMETER MINIMUM MAXIMUM UNITS * t20a *t 20b Data word parity bit to MES ERR assertion 1 Command word parity bit to MES ERR assertion RT to RT transfer 2 23.50 55.4 23.63 55.5 s s Notes: 1. Measured from last data word mid-bit parity crossing. 2. No response from transmitter. * Supplied as a design limit but not guaranteed or tested. RTI-34 ADDR IN (10:0) DATA(15:0) UT1553B RTI CONTROL HOST SUBSYSTEM UT63M125 1553 TRANSCEIVER 1553 BUS A 1553 BUS B Figure 21. RTI General System Diagram (Idle low interface) IN O IN Z BIPHASE CHANNEL A OUT O OUT Z RTI IN O IN Z TXINHB OUT O OUT Z TIMERON LOGIC CH A/B TXIN- RXOUT RXOUT CHANNEL A TXIN TXIN UTMC 63M125 RXOUT RXOUT CHANNEL B TXIN TXIN BIPHASE CHANNEL B Figure 22. RTI Transceiver Interface Diagram RTI-35 RTI MC/SA MCSA0 MCSA1 MCSA2 MCSA3 MCSA4 COMSTR BRDCST ILLEGAL COMMAND DECODER RCV XMIT ILL COMM Figure 23. Mode Code/Subaddress Illegalization Circuit BIPHASE IN C COMSTR RC DMARQ MEMCK RC RRD/RWR COMMAND PD DATA PD DATA P ADDR OUT BUS DATA BUS STATUS BIPHASE OUT Figure 24. Receive Command with Two Data Words SS STATUS WORD P VALID VALID RTI-36 BIPHASE IN CS COMMAND P COMSTR XMIT DMARQ MEMCK RCS RRD/RWR ADDR OUT BUS DATA BUS STATUS BIPHASE OUT SS VALID VALID STATUS WORD P DS DATA WORD P DS DATA WORD Figure 25. Transmit Command with Two Data Words RTI-37 PACKAGE OUTLINE DRAWINGS L K J H G F E D C B A L K J H G F E D C B A 1 L K J H G F E D C B A 2 L K L K L K J L K J L K J L K L K L1 K1 J1 H1 L1 K1 J1 H1 G1 F1 E1 D1 C1 B1 A1 11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 ADDR OUT 0 MCSA 0 ADOEN MCSA 2 ILL COMM CH A/B 2MHz BIPHASE OUT A EXT TEST BIPHASE OUT B BIPHASE OUT B G F E G F E G1 F1 E1 D1 C B A 3 B A 4 F1 F2 F3 F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 C B A 6 C B A 7 B A 8 J1 J2 J5 J6 J7 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 C1 B A 9 B1 A1 10 B A 5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 DATA I/O 0 DATA I/O 2 DATA I/O 3 DATA I/O 5 DATA I/O 8 DATA I/O 9 TA 1 DATA I/O 12 DATA I/O 13 DATA I/O 14 DATA I/O 15 ADDR IN 9 ADDR IN 10 DATA I/O 1 DATA I/O 4 DATA I/O 7 DATA I/O 11 TA 2 TA 3 TA 4 VDD RCV C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 ADDR OUT 9 ADDR OUT 10 DATA I/O 6 TA 0 DATA I/O 10 TALEN/PARITY CTRL ADDR OUT 8 ADDR IN 8 MES ERR MEMCK ADDR IN 6 ADDR OUT 7 ADDR OUT 6 CS RD/WR RRD/RWR ADDR OUT 5 ADDR IN 7 ADDR IN 5 RCS VSS DMARQ ADDR IN 4 ADDR OUT 4 ADDR IN 3 BIPHASE IN A Z MRST TIMERON ADDR OUT 3 ADDR IN 2 BIPHASE IN A O XMIT ADDR OUT 2 ADDR OUT 1 MCSA 3 COMSTR STATUS BIPHASE IN B Z BRDCST ADDR IN 1 VSS ADDR IN 0 MCSA 1 MCSA 4 MC/SA BCEN BIPHASE OUT A Z EXT TST CH SEl A/B BIPHASE IN B O 12MHz Figure 26a. UT1553B RTI Pingrid Array Configuration (Bottom View) RTI-38 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ADDR IN 5 ADDR OUT 5 ADDR IN 4 ADDR OUT 4 ADDR IN 3 ADDR OUT 3 ADDR IN 2 ADDR OUT 2 ADDR IN 1 ADDR OUT 1 ADDR OUT 0 VSS ADDR IN 0 MCSA0 ADOEN MCSA1 MCSA2 MCSA3 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 MCSA 4 38 ILL COMM 39 MC/SA 40 COMSTR 41 STATUS 42 2MHz BCEN 43 CH A/B 44 BIPHASE OUT A O 45 BIPHASE OUT A Z 46 EXT TEST 47 BIPHASE OUT B Z 48 EXT TST CH SEL A/B49 BIPHASE OUT B O 50 BIPHASE IN B O 51 BIPHASE IN B Z 52 12MHz 53 BRDCST 54 BIPHASE IN A O XMIT BIPHASE IN A Z MRST TIMERON VSS RCS CS RRD/RWR RD/WR DMARQ MEMCK MES ERR CTRL RCV TALEN/PARITY DATA I/O 15 VDD 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 DATA I/O 14 TA4 DATA I/O 13 TA3 DATA I/O 12 TA2 DATA I/O 11 TA1 DATA I/O 10 TA0 DATA I/O 9 DATA I/O 8 DATA I/O 7 DATA I/O 6 DATA I/O 5 DATA I/O 4 DATA I/O 3 DATA I/O 2 73 74 75 76 77 78 79 80 81 82 83 84 DATA I/O 1 DATA I/O 0 ADDR IN 10 ADDR OUT 10 ADDR IN 9 ADDR OUT 9 ADDR IN 8 ADDR OUT 8 ADDR IN 7 ADDR OUT 7 ADDR IN 6 ADDR OUT 6 Figure 26b. UT1553B RTI Chip Carrier Configuration (Top View) RTI-39 Package Selection Guide Product BCRT BCRTM BCRTMP RTI 24-pin DIP (single cavity) 36-pin DIP (dual cavity) 68-pin PGA 84-pin PGA 144-pin PGA 84-lead LCC 36-lead FP (dual cavity) (50-mil ctr) 84-lead FP 132-lead FP NOTE: RTMP RTR RTS XCVR X X X X X X X X X1 X X1 X X X X X X 1. 84LCC package is not available radiation-hardened. Packaging-1 D 1.565 0.025 0.080 REF. (2 Places) -A- A 0.130 MAX. Q 0.050 0.010 L 0.130 0.010 A 0.040 REF. E 1.565 0.025 -B- 0.100 REF. (4 Places) PIN 1 I.D. (Geometry Optional) e 0.100 TYP. R P N M L K J H G F E D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIN 1 I.D. (Geometry Optional) TOP VIEW -CA (Base Plane) b 0.018 0.002 0.030 C A B 0.010 C 2 SIDE VIEW 1 D1/E1 1.400 BOTTOM VIEW 0.003 MIN. TYP. Notes: 1. True position applies to pins at base plane (datum C). 2. True position applies at pin tips. 3. All package finishes are per MIL-M-38510. 4. Letter designations are for cross-reference to MIL-M-38510. 144-Pin Pingrid Array Packaging-2 D/E 1.525 0.015 SQ. D1/E1 0.950 0.015 SQ. PIN 1 I.D. (Geometry Optional) e 0.025 A 0.110 0.006 A SEE DETAIL A LEAD KOVAR TOP VIEW S1 0.005 MIN. TYP. L 0.250 MIN. REF. A C 0.005 + 0.002 - 0.001 SIDE VIEW 0.014 MAX. REF. (At Braze Pads) DETAIL A 0.018 MAX. REF. BOTTOM VIEW A-A Notes: 1. All package finishes are per MIL-M-38510. 2. Letter designations are for cross-reference to MIL-M-38510. 132-Lead Flatpack (25-MIL Lead Spacing) Packaging-3 D/E 1.150 0.015 SQ. A 0.115 MAX. A1 0.080 0.008 A PIN 1 I.D. (Geometry Optional) TOP VIEW A SIDE VIEW L/L1 0.050 0.005 TYP. h 0.040 x 45_ REF. (3 Places) B1 0.025 0.003 e 0.050 J 0.020 X 455 REF. e1 0.015 MIN. PIN 1 I.D. (Geometry Optional) BOTTOM VIEW A-A Notes: 1. All package finishes are per MIL-M-38510. 2. Letter designations are for cross-reference to MIL-M-38510. 84-LCC Packaging-4 D/E 1.810 0.015 SQ. D1/E1 1.150 0.012 SQ. A 0.110 0.060 PIN 1 I.D. (Geometry Optional) A e 0.050 b 0.016 0.002 SEE DETAIL A A LEAD KOVAR TOP VIEW L 0.260 MIN. REF. C 0.007 0.001 SIDE VIEW S1 0.005 MIN. TYP. 0.018 MAX. REF. 0.014 MAX. REF. (At Braze Pads) BOTTOM VIEW A-A Notes: 1. All package finishes are per MIL-M-38510. 2. Letter designations are for cross-reference to MIL-M-38510. DETAIL A 84-Lead Flatpack (50-MIL Lead Spacing) Packaging-5 D 1.100 0.020 -A- A 0.130 MAX. Q 0.050 0.010 A L 0.130 0.010 E 1.100 0.020 -B- PIN 1 I.D. (Geometry Optional) TOP VIEW -C(Base Plane) e 0.100 TYP. L K J H G D1/ F E D 1.000 A b 0.018 0.002 0.030 C A B 0.010 C 2 SIDE VIEW 1 PIN 1 I.D. (Geometry Optional) BOTTOM VIEW A-A 1 2 3 4 5 6 7 8 9 10 11 0.003 MIN. Notes: 1. True position applies to pins at base plane (datum C). 2. True position applies at pin tips. 3. All packages finishes are per MIL-M-38510. 4. Letter designations are for cross-reference to MIL-M-38510. 84-Pin Pingrid Array Packaging-6 D 1.100 0.020 -A- A 0.130 MAX. Q 0.050 0.010 A L 0.130 0.010 E 1.100 0.020 -B- PIN 1 I.D. (Geometry Optional) TOP e 0.100 TYP. -C(Base Plane) A b 0.010 0.002 0.030 C A B 0.010 C 2 SIDE VIEW 1 L K J H G F E D C B A 123456 PIN 1 I.D. (Geometry Optional) 7 8 9 10 11 D1/E1 1.00 0.003 MIN. TYP. BOTTOM VIEW A-A Notes: 1 True position applies to pins at base plane (datum C). 2 True position applies at pin tips. 3. All packages finishes are per MIL-M-38510. 4. Letter designations are for cross-reference to MIL-M-38510. 68-Pin Pingrid Array Packaging-7 E 0.750 0.015 L 0.490 MIN. b 0.015 0.002 D 1.800 0.025 e 0.10 PIN 1 I.D. (Geometry Optional) TOP VIEW c 0.008 A 0.130 MAX. END VIEW Notes: 1 All package finishes are per MIL-M-38510. 2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be used. 3. Letter designations are for cross-reference to MIL-M-38510. + 0.002 - 0.001 Q 0.080 0.010 (At Ceramic Body) 36-Lead Flatpack, Dual Cavity (100-MIL Lead Spacing) Packaging-8 E 0.700 + 0.015 L 0.330 MIN. b 0.016 + 0.002 D 1.000 0.025 e 0.050 PIN 1 I.D (Geometry Optional) TOP + 0.002 c 0.007 - 0.001 A 0.100 MAX. Q 0.070 + 0.010 (At Ceramic Body) END Notes: 1. All package finishes are per MIL-M-38510. 2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be used. 3. Letter designations are for cross-reference to MIL-M-38510. 36-Lead Flatpack, Dual Cavity (50-MIL Lead Spacing) Packaging-9 E 0.590 0.012 S1 0.005 MIN. S2 0.005 MAX. e 0.100 D 1.800 0.025 b 0.018 0.002 PIN 1 I.D. (Geometry Optional) TOP VIEW A 0.155 MAX. SIDE VIEW L/L1 0.150 MIN. C 0.010 +- 0.002 0.001 E1 0.600 + 0.010 (At Seating Plane) END VIEW Notes: 1. All package finishes are per MIL-M-38510. 2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be used. 3. Letter designations are for cross-reference to MIL-M-38510. 36-Lead Side-Brazed DIP, Dual Cavity Packaging-10 E 0.590 0.015 S1 0.005 MIN. S2 0.005 MAX. e 0.100 D 1.200 0.025 b 0.018 0.002 PIN 1 I.D. (Geometry Optional) A 0.140 MAX. SIDE VIEW L/L1 0.150 MIN. TOP VIEW + 0.002 C 0.010 - 0.001 E1 0.600 + 0.010 (At Seating Plane) Notes: 1. All package finishes are per MIL-M-38510. 2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be used. 3. Letter designations are for cross-reference to MIL-M-38510. END VIEW 24-Lead Side-Brazed DIP, Single Cavity Packaging-11 ORDERING INFORMATION UT1553B RTI Remote Terminal Interface: 5962 * * * * * * Lead Finish: (A) = Solder (C) = Gold (X) = Optional Case Outline: (Z) = 84 pin PGA Class Designator: (B) = Jan Class Q Device Type 01 = 10% to 35% Clock Duty Cycle Drawing Number: JM38510/555 Total Dose: (-) = None Federal Stock Class Designator: No options Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). UT1553B RTI Remote Terminal Interface UT1553B - * * * * Lead Finish: (A) = Solder (C) = Gold (X) = Optional Screening: (C) = Military Temperature (P) = Prototype Package Type: (G) = 84 pin PGA Modifier: RTI = 10% to 35% Clock Duty Cycle UTMC Core Part Number Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Mil Temp range flow per UTMC's manufacturing flows document. Devices are tested at -55C, room temperature, and 125C. 4. Prototpe flow per UTMC's document manufacturing flows and are tested at 25C only. Lead finish is GOLD only. 5. Prototypes and reduced high-reliability devices are only available with 40% to 60% clock duty cycle. |
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